SiFive, designer of processors RISC-V ended up in Intel’s sights (unsuccessful for now), is working on a successor to the core Performance P550 which “will set a new standard for the highest efficiency RISC-V processor available.” The new project aims at improve performance by 50% putting the Cortex-A78 di arm and design Rocket Lake at Intel in the viewfinder in terms of single-core performance. This was said by James Prior, SiFive’s senior director of marketing and communications, at The Register and Tom’s Hardware.
Waiting for the RISC-V Summit in December where the company is expected to reveal more details, SiFive seems convinced it can make RISC-V – una ISA open source e royalty-free – a viable alternative to x86 and arm solutions relatively quickly and in every market segment.
According to what reported by The Register, the new core of SiFive will allow you to create clusters with four times the resources, from the L3 cache (going from 4 to 16 MB) to the cores (from 4 to 16 cores). Furthermore, it is referred to as an operating frequency fino a 3,5 GHz compared to the P550’s 2.4 GHz. Otherwise there shouldn’t be many differences in terms of architecture compared to the P550.
According to Prior, the CPUs based on the new core will therefore be able to find space in PCs and servers, also scaling to the mobile world and embedded devices. Customers who intend to take advantage of the new core will be able to create custom solutions with support DDR5 and PCIe 5.0, but also scalable up to 128 cores to handle the heaviest loads. On the other hand, it is no mystery that RISC-V also points to the world “high-performance computing” (HPC), as indicated by RISC-V International, the organization overseeing the development of the RISC-V ISA.